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SUMMARY:Engineering Teaching Community (Faculty)
DESCRIPTION:During the chaos of a quarter\, is it hard to find time to reflect and improve as an instructor? Would you like to be a part of an inclusive\, supportive group of engineering instructors who do this in community? ETC is for sharing teaching experiences\, classroom ideas\, research on learning\, and methods that support instructors and students. All are welcome\, and lunch is provided. Please reach out to Jenny Quynn with questions.
URL:https://live-events-ucsc.pantheonsite.io/event/engineering-teaching-community-faculty/2026-05-27/
LOCATION:Jack Baskin Engineering\, Baskin Engineering 1156 High Street\, Santa Cruz\, CA\, 95064
CATEGORIES:Meetings & Conferences,Training
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DTSTART;TZID=America/Los_Angeles:20260527T180000
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SUMMARY:Build better chips
DESCRIPTION:Verify faster. Build better chips.\nSemiconductor Design Info Session\nExplore the fast-paced world of semiconductor design and verification\, and how advanced tools—including AI—are transforming the industry. \nAt this info session\, instructor Mandar Munishwar\, a formal verification architect at the Intel Data Center and AI Division\, will discuss his SystemVerilog Assertions and Formal Verification course which prepares you to write assertions\, create verification test plans\, and use simulation and formal tools to catch design issues early and improve first-pass silicon success. \nDiscover how this hands-on\, lab-based course builds practical skills in SystemVerilog\, assertion-based verification\, and formal verification using industry-standard tools like VCS and VC Formal. You’ll better understand emerging trends such as AI-assisted assertion generation and debugging. \nSee how this course in the UCSC Silicon Valley Extension Semiconductor Design program can help advance your career in chip design and verification engineering. \nClaim your seat! \nYou might also be interested in: \n\nPhysical Design Flow From Netlist to GDSII | June 5\nPractical Design with Xilinx FPGAs | June 15\nSystem and Functional Verification Using UVM | June 18\nSystemVerilog Assertions and Formal Verification | June 22\nAdvanced Verification with SystemVerilog OOP Testbench | June 25\nComprehensive Signal and Power Integrity for High-Speed Digital Systems | June 25
URL:https://live-events-ucsc.pantheonsite.io/event/build-better-chips/
LOCATION:Silicon Valley Campus\, 3175 Bowers Avenue\, Santa Clara\, CA\, 95054\, United States
CATEGORIES:Lectures & Presentations,Meetings & Conferences,Training
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